PRODUCT SPECIFICATION

FAN5067

REV. 1.0.1 5/2/02

11

FAN5067 ACPI Control Lines

As already discussed, the FAN5067 outputs are controlled

by the three ACPI control lines, SLP_S3, SLP_S5 and

PWROK, as summarized in Tables 1 and 2. System design-

ers must in particular be careful to ensure that their system is

designed with SLP_S5, not SLP_S5; if SLP_S5 is used, it

must be inverted before being used with the FAN5067.

The control lines have internal pull-ups of approximately

40µA, and so can be controlled by open collector drivers if

desired. In a noisy system, it may be desirable to filter these

lines, which can be done with a 1K

Ω resistor and a small

capacitor.

FAN5067 Dynamic Operation

The FAN5067 is designed to minimize the output capaci-

tance required to hold up the various output lines during

transitions between different states. Thus in particular, the

adjustable dual output has guaranteed minimum overlap

time, the time (as shown in Figure 2) during a state transition

during which both main and standby are connected to the

output. This overlap time guarantees that a power source is

always connected to the output, so that there will be no dip in

the output voltage during state transitions. There is also a

maximum overlap time, to ensure that the standby power

doesn’t have to source main power very long, thus minimiz-

ing thermal stress on the standby device.

The dual output is different because it is powered by both a

linear regulator and a switch. If the linear regulator were to

turn on while the switch is on (or vice versa) the linear regu-

lator would supply power to the main line through the

switch. For this reason, the linear regulator must be off

before the switch is on, and vice versa. Thus, this output has

guaranteed minimum deadtime when both linear regulator

and switch are off. During this time, the output capacitor

must hold up the load, and so there is also a specified maxi-

mum deadtime, allowing a maximum necessary capacitance

to be selected, see below.

Stability

As with all linear regulators, the FAN5067’s linear regulators

require a minimum load. With the exception of the 3.3V dual

output, however, all of these minimum loads are internal to

the FAN5067. The dual output requires a minimum load of

50mA; if a situation may occur in which the load is less than

50mA, additional steps may be necessary to ensure stability.

Furthermore, depending on location, it may be necessary to

bypass the drain (or collector) of the linear regulator with a

low ESR capacitor for stability. As a rule of thumb, if the

pass element is more than 1” from its power source, it should

have a bypass.

Softstart

Pin 10 of the FAN5067 functions as a softstart. When power

is first applied to the chip, a constant current is applied from

the pin into an external capacitor, linearly ramping up the

voltage. This ramp in turn controls the internal reference of

the FAN5067. providing a softstart for the linear regulators.

The actual state of the FAN5067 on power up will be deter-

mined by the state of its control lines.

The switches in the system must be either on or off, and so

softstart has no effect on their characteristics: if the appropri-

ate control signals are asserted, they will turn on at once.

The softstart is effective only during power on. During a

transition between states, such as from S5

→ S0, the linear

regulators are not softstarted.

It is important to note that the softstart pin is not an enable;

pulling it low will not necessarily turn off all outputs.

Charge Pump

In main power operation, the FAN5067 is run from the +12V

main supply. This supply also provides voltage to the various

MOSFET gates. However, during standby, this supply is off.

To provide power to the chip and the appropriate gates, the

FAN5067 incorporates a free-running charge pump. As

shown in Figure 4, and in the block diagram on the front

page, a capacitor attached between pins 1 and 2 of the

FAN5067 acts as a charge pump with internal diodes. The

charge pump output is internally diode or’red with the 12V

input. The 12V input must have a series diode to prevent

back-feeding the charge pump to the + 12V main when in

standby. The 12V input line needs a bypass capacitor for

high-frequency noise rejection. If desired, the system may be

operated without the 12V or the diode; however, the bypass

capacitor must still be present.

Overcurrent

The FAN5067 does not directly detect current through the

devices that power its outputs. Instead, it monitors the output

voltages. In the event of a hard short, the voltage drops

below 80% of nominal, and all outputs are latched off, and

remain off until 5V standby power is recycled. The overcur-

rent latch off is delayed by 150µsec to prevent nuisance trips.

During softstart, the overcurrent voltage monitors are kept

proportional to the reference, to avoid tripping overcurrent

during startup.

In the S5 state, when the memory outputs are off, the voltage

monitors on the memory lines are disabled, to prevent trip-

ping the overcurrent. When turning these lines back on from

the S5 state, overcurrent is prevented from tripping because

the S3 state is blocked. See Table 2.

If the adjustable dual is not used, its feedback line, pin 12,

must be connected to 5V STBY, to prevent an overcurrent

trip.