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ADS5402 Arkusz danych(PDF) 5 Page - Texas Instruments

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Numer części ADS5402
Szczegółowy opis  Dual Channel 12-Bit 900Msps Analog-to-Digital Converter
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5402 Arkusz danych(HTML) 5 Page - Texas Instruments

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ADS5409
www.ti.com
SLAS935 – MAY 2013
PACKAGE/ORDERING INFORMATION
SPECIFIED
LEAD/
TRANSPORT
ECO
ORDERING
PACKAGE-
PACKAGE
PACKAGE
PRODUCT
TEMPERATURE
BALL
MEDIA,
LEAD
DESIGNATOR
MARKING
NUMBER
PLAN(2)
RANGE
FINISH
QUANTITY
GREEN
ADS5409IZAY
Tray
ADS5409
196-BGA
ZAY
–40C to 85C
ADS5409I
(RoHS & no
ADS5409IZAYR
Tape and Reel
Sb/Br)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
MAX
Supply voltage range, AVDD33
–0.5
4
V
Supply voltage range, AVDDC
–0.5
2.3
V
Supply voltage range, AVDD18
–0.5
2.3
V
Supply voltage range, DVDD
–0.5
2.3
V
Supply voltage range, DVDDLVDS
–0.5
2.3
V
Supply voltage range, IOVDD
–0.5
4
V
INA/B_P, INA/B_N
–0.5
AVDD33 + 0.5
V
CLKINP, CLKINN
–0.5
AVDDC + 0.5
V
Voltage applied to input pins
SYNCP, SYNCN
–0.5
AVDD33 + 0.5
V
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
–0.5
IOVDD + 0.5
V
Operating free-air temperature range, TA
–40
85
°C
Operating junction temperature range, TJ
150
°C
Storage temperature range
–65
150
°C
ESD, Human Body Model
2
kV
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
ADS5409
THERMAL METRIC(1)
nFBGA
UNITS
196 PINS
θJA
Junction-to-ambient thermal resistance(2)
37.6
θJCtop
Junction-to-case (top) thermal resistance(3)
6.8
θJB
Junction-to-board thermal resistance(4)
16.8
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.2
ψJB
Junction-to-board characterization parameter(6)
16.4
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
Copyright © 2013, Texas Instruments Incorporated
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