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ADS5402 Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS5402 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 41 page N N-1 CLKINP Data Latency ? Clock Cycles SAMPLE N DACLKP DBCLKP N+1 tPD DCLK edges are centered within the data valid window tsu th DA[11:0]P/N DB[11:0]P/N OVRAP/N ORVBP/N CLKIN, DCLK are differential: Only the ‘P’ positive signal shown for clarity ADS5409 SLAS935 – MAY 2013 www.ti.com Figure 3. Timing Diagram for 12-bit DDR Output 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS5409 |
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