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ADS5404 Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS5404 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 41 page ADS5409 www.ti.com SLAS935 – MAY 2013 ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 900Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OVER-DRIVE RECOVERY ERROR Recovery to within 5% (of final value) for 6dB Output Input overload recovery 2 overload with sine wave input Clock SAMPLE TIMING CHARACTERISTICS rms Aperture Jitter Sample uncertainty 100 fs rms ADC sample to digital output, auto correction disabled 38 Clock Cycles ADC sample to digital output, auto correction enabled 50 Data Latency Sampling ADC sample to digital output, Decimation filter 74 Clock enabled, Auto correction disabled Cycles Clock Over-range Latency ADC sample to over-range output 12 Cycles ELECTRICAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE 0.7 x High-level input voltage V IOVDD All digital inputs support 1.8V and 3.3V logic levels. 0.3 x Low-level input voltage V IOVDD High-level input current –50 200 µA Low-level input current –50 50 µA Input capacitance 5 pF DIGITAL OUTPUTS – SDO IOVDD – Iload = -100µA 0.2 High-level output voltage V 0.8 x Iload = -2mA IOVDD Iload = 100µA 0.2 Low-level output voltage V 0.22 x Iload = 2mA IOVDD DIGITAL INPUTS – SYNCP/N VID Differential input voltage 250 350 450 mV VCM Input common mode voltage 1.125 1.2 1.375 V tSU 500 ps DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, DB[11:0]P/N, DBCLKP/N, OVRBP/N VOD Output differential voltage Iout = 3.5mA 250 350 450 mV VOCM Output common mode voltage Iout = 3.5mA 1.125 1.25 1.375 V Fs = 900Msps, Data valid to zero-crossing of tsu 230 336 ps DACLK, DBCLK Fs = 900Msps, Zero-crossing of DACLK, th 230 380 ps DBCLK to data becoming invalid Fs = 900Msps, CLKIN falling edge to tPD 3.36 3.69 3.92 ns DACLK, DBCLK rising edge tRISE 10% - 90% 100 150 200 ps tFALL 90% - 10% 100 150 200 ps Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS5409 |
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