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ADG726BSU Arkusz danych(PDF) 5 Page - Analog Devices

Numer części ADG726BSU
Szczegółowy opis  16-/32-Channel, 4  1.8 V to 5.5 V, 2.5 V Analog Multiplexers
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ADG726BSU Arkusz danych(HTML) 5 Page - Analog Devices

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REV. 0
–5–
ADG726/ADG732
TIMING CHARACTERISTICS1, 2, 3
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
0
ns min
CS to WR Setup Time
t2
0
ns min
CS to WR Hold Time
t3
10
ns min
WR Pulsewidth
t4
10
ns min
Time between
WR Cycles
t5
5
ns min
Address, Enable Setup Time
t6
2
ns min
Address, Enable Hold Time
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD).
3Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
t1
t2
t3
t4
t5
t6
CS
WR
A0, A1, A2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while
WR is held low, the latches are transparent and the
switches respond to changing the address and enable the inputs.
Input data is latched on the rising edge of
WR. The ADG726
has two
CS inputs. This enables the part to be used either as a
dual 16-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie
CSA and
CSB together.


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