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ADT7411 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części ADT7411
Szczegółowy opis  SPI짰-/I2C짰-Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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ADT7411 Arkusz danych(HTML) 5 Page - Analog Devices

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ADT7411
Rev. B | Page 5 of 36
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
5.5
V
VDD Settling Time
50
ms
VDD settles to within 10% of its final voltage level.
IDD (Normal Mode)8
3
mA
VDD = 3.3 V, VIH = VDD and VIL = GND.
2.2
3
mA
VDD = 5 V, VIH = VDD and VIL = GND.
IDD (Power-Down Mode)
10
μA
VDD = 3.3 V, VIH = VDD and VIL = GND.
10
μA
VDD = 5 V, VIH = VDD and VIL = GND.
Power Dissipation
10
mW
VDD = 3.3 V. Using normal mode.
33
μW
VDD = 3.3 V. Using shutdown mode.
1 See the Terminology section.
2 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3 Guaranteed by design and characterization, not production tested.
4 The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative effect on the EMC behavior of the part.
5 Guaranteed by design. Not tested in production.
6 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
7 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
8 IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
SCL
t4
t2
t1
t3
t5
t6
SDA
DATA IN
SDA
DATA OUT
t7
Figure 2. I2C Bus Timing Diagram
t1
t2
t3
t5
t6
t4
t7
t8
D7
CS
SCLK
DIN
DOUT
D6
D5
D4
D3
D2
D1
D0
X
X
XXXXX
X
X
X
X
X
X
X
X
X
D7D6
D5
D4D3D2D1
D0
Figure 3. SPI Bus Timing Diagram
200µA
IOH
1.6V
TO
OUTPUT
PIN
CL
50pF
200µA
IOL
Figure 4. Load Circuit for Access Time and Bus Relinquish Time


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