DAC7545

6

SBAS150A

www.ti.com

FIGURE 5. 8-Bit Processor Interface.

DAC7545

CS

DB

0

DB

7

WR

DB

8

DB

11

Latch

CS

WR

44

8

Q

1

(2)

8-Bit Data Bus

Q

0

(1)

Address Bus

Address

Decode

CPU

WR

DB

7

DB

0

A

15

A

0

NOTES: (1) Q

(2) Q

FIGURE 4. Digitally Controlled Gain Block.

R

FB

DAC7545

AGND

DGND

OUT 1

DB

V

IN

WR

V

OUT

CS

16

+5V

NOTE: There must be

at least 1LSB loaded in

the DAC or the amp will

saturate due to the lack

of feedback.

OPA111

17

18

19

V

–V

IN

DB

11

+

2

DB

10

+

4

DB

9

+ ••• +

8

DB

0

4096

20

DIGITALLY-CONTROLLED GAIN BLOCK

Figure 4 shows a circuit for a digitally-controlled gain block.

The feedback for the op amp is made up of the FET switch

and the R-2R ladder. The input resistor to the gain block is

feedback loop, a zero code into the DAC will result in the op

amp having no feedback, and a saturated op amp output.

APPLICATION HINTS

CMOS DACs, such as the DAC7545, exhibit a code-depen-

dent out resistance. The effect of this is a code-dependent

differential nonlinearity at the amplifier output that depends on

upon the potential of OUT 1 and AGND being exactly equal to

each other. Usually the DAC is connected to an external op

amp with the noninverting input connected to AGND. The op

Suitable op amps are the OPA37 and the OPA627 for fixed

reference applications and low-bandwidth requirement; the

wide bandwidth, high slew rate, or fast-settling applications, the

OPA604 or 1/2 OPA2604 are recommended.

this prevents noise from triggering the high impedance digital

input. It is suggested that the unused digital inputs also be

prevent the accumulation of static charge if the PC card is

unplugged from the system. In addition, in systems where

the AGND to DGND connection is on a backplane, it is

recommended that two diodes be connected in inverse

parallel between AGND and DGND.

INTERFACING

TO MICROPROCESSORS

The DAC7545 can be directly interfaced to either an 8- or 16-

bit microprocessor through its 12-bit wide data latch using

An 8-bit processor interface is shown in Figure 5. It uses two

memory addresses: one for the lower 8 bits and one for the

upper 4 bits of data into the DAC via the latch.