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TLC1543QDB Arkusz danych(PDF) 10 Page - Texas Instruments |
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TLC1543QDB Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 33 page www.ti.com TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q SLAS052G – MARCH 1992 – REVISED JANUARY 2006 OPERATING CHARACTERISTICS (continued) over recommended operating free-air temperature range, V CC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) TEST MIN TYP (1) MAX UNIT CONDITIONS TLC1542C, I, or Q See (4) ±1 LSB EZS Zero-scale error, see (3) TLC1543C, I, or Q See (4) ±1 LSB TLC1542M See (4) ±1 LSB TLC1542C, I, or Q See (4) ±1 LSB EFS Full-scale error, see (3) TLC1543C, I, or Q See (4) ±1 LSB TLC1542M See (4) ±1 LSB TLC1542C, I, or Q ±1 LSB Total unadjusted error, see (5) TLC1543C, I, or Q ±1 LSB TLC1542M ±1 LSB ADDRESS = 1011 512 Self-test output code, see Table 3 and (6) ADDRESS = 1100 0 ADDRESS = 1101 1023 See timing tconv Conversion time 21 µs diagrams 21 See timing +10 I/O tc Total cycle time (access, sample, and conversion) µs diagrams and (7) CLOCK periods See timing I/O CLOCK tacq Channel acquisition time (sample) 6 diagrams and (7) periods tv Valid time, DATA OUT remains valid after I/O CLOCK ↓ See Figure 6 10 ns td(I/O-DATA) Delay time, I/O CLOCK ↓ to DATA OUT valid See Figure 6 240 ns td(I/O-EOC) Delay time, tenth I/O CLOCK ↓ to EOC↓ See Figure 7 70 240 ns td(EOC-DATA) Delay time, EOC ↑ to DATA OUT (MSB) See Figure 8 100 ns tPZH, tPZL Enable time, CS ↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs tPHZ, tPLZ Disable time, CS ↑ to DATA OUT (high impedance) See Figure 3 150 ns tr(EOC) Rise time, EOC See Figure 8 300 ns tf(EOC) Fall time, EOC See Figure 7 300 ns tr(DATA) Rise time, data bus See Figure 6 300 ns tf(DATA) Fall time, data bus See Figure 6 300 ns Delay time, tenth I/O CLOCK ↓ to CS↓ to abort td(I/O-CS) 9 µs conversion (see Note (8)) (3) Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference between 1111111111 and the converted output for full-scale input voltage. (4) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+-Vref-); however, the electrical specifications are no longer applicable. (5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors. (6) Both the input address and the output codes are expressed in positive logic. (7) I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6) (8) Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock (1.425 µs) after the transition. 10 Submit Documentation Feedback |
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