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74HCT02DB Arkusz danych(PDF) 6 Page - NXP Semiconductors

Numer części 74HCT02DB
Szczegółowy opis  Quad 2-input NOR gate
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74HCT02DB Arkusz danych(HTML) 6 Page - NXP Semiconductors

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74HC_HCT02
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 4 September 2012
6 of 16
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
[1]
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD  VCC2  fi  N+  (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
 (C
L  VCC
2
 f
o) = sum of outputs.
11. Waveforms
74HCT02
tpd
propagation delay
nA, nB to nY; see Figure 6
[1]
VCC = 4.5 V
-
11
19
24
29
ns
VCC = 5.0 V; CL =15pF
-
9
-
-
-
ns
tt
transition time
VCC = 4.5 V; see Figure 6
[2]
-
7
15
19
22
ns
CPD
power dissipation
capacitance
per package;
VI =GND to VCC  1.5 V
[3]
-24-
-
-
pF
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
25
C
40 C to +125 C Unit
Min
Typ
Max
Max
(85
C)
Max
(125
C)
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Input to output propagation delays
001aai814
nA, nB input
VI
GND
VOH
VOL
nY output
tTHL
tTLH
VM
VM
VX
VY
tPHL
tPLH
Table 8.
Measurement points
Type
Input
Output
VM
VM
VX
VY
74HC02
0.5VCC
0.5VCC
0.1VCC
0.9VCC
74HCT02
1.3 V
1.3 V
0.1VCC
0.9VCC


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