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FM25C640U Rev. B

The FM25C640U is also capable of a 32 byte PAGE WRITE

operation. Page write is performed similar to byte write operation

described above. During a Page write operation, after the first byte

of data, additional bytes (up to 31 bytes) can be input, before

bringing the /CS pin high to start the programming. After receipt of

each byte of data, the EEPROM internally increments the four low

order address bits (A4-A0) by one. The high order address bits

(A12-A5) will remain constant. If the master should transmit more

than 32 bytes of data, the address counter (A4-A0) will “roll over”

and the previously loaded data will be reloaded. See

Figure 11.

FIGURE 11. Page Write

CS

SI

SO

Write

Opcode

High Addr

Byte

Low Addr

Byte

Data

(1)

Data

(2)

Data

(32)

High Z

/CS

SI

SO

WRSR

Op-Code

SR Data

xxxxBP1BP0xx

FIGURE 12. Write Status Register

BP0

SCK

SI

SO

/CS

/CS

SI

SO

INVALID CODE

At the completion of a write cycle the EEPROM is automatically

returned to the write disabled state. Note that if the EEPROM is not

write enabled (WEN=0) before issuing the WRITE instruction, the

EEPROM will ignore the WRITE instruction and return to the

standby state when /CS is brought high.

WRITE STATUS REGISTER (WRSR):

The Write Status Register (WRSR) instruction provides write

access to the status register. This instruction is used to set Block

Write protection to a portion of the array as defined under Table

4. During a WRSR instruction only Bit3 (BP1) and Bit2 (BP0) can

be written with valid information while other bits are ignored.

Following is the format of WRSR data:

Status Register Write Data

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

7

6

54

32

1

0

X

X

X

X

BP1

BP0

X

X

X = Don’t Care

Note that the first four bits are don’t care bits followed by BP1 and

BP0 and two more don’t care bits.

WRSR instruction is enabled only when /WP pin is held high and

the EEPROM is write enabled previously (via WREN instruction).

WRSR command requires the following sequence. The /CS pin is

pulled low to select the EEPROM and then the WRSR opcode is

transmitted on the SI pin followed by the data to be programmed.

See

Figure 12.

Programming will start after the /CS pin is forced back to a high

level. As in the WRITE instruction the LOW to HIGH transition of

the /CS pin must occur during the SCK low time immediately after

clocking in the last don’t care bit. See

Figure 13.

FIGURE 13. Start WRSR Condition

At the completion of this instruction the EEPROM is automatically

returned to write disabled state.

INVALID OPCODE

If an invalid code is received, then no data is shifted into the

EEPROM, and the SO data output pin remains high impedance

state until a new /CS falling edge reinitializes the serial communi-

cation. See

Figure 14.

FIGURE 14. Invalid Op-Code