UG-486

Evaluation Board User Guide

Rev. 0 | Page 4 of 8

DATA I/O

There are two data I/O pins on each side of the board. For

example, examining Channel A on Side 1, Figure 3 shows the

following structures, starting from each I/O connector:

•

A position for a pull-down resistor or termination to be

installed in R2A and R4A.

•

A 0 Ω resistor at R6A connects the trace to the SMA

connector and termination. This allows extra trace length

and components to be removed when capacitance must

be controlled.

•

R8A and C1A are available for a pull-up or pull-down

resistor or for a capacitive load when the I/O is an output.

•

There is the P1A test point, with a 200mil pitch. This is for

hard wiring inputs or installing a Tektronix active probe

header.

•

Position R10A allows interconnection of Channel A and

Channel B. Inputs on the same side can share a single off

board connection, or an output signal can be wrapped back

to an input.

The same set of structures is present on each channel, allowing

a wide range of tests to be conducted with minimum config-

uration.

EMI MITIGATION

The PCB implements EMI mitigation techniques discussed

in the AN-0971 Application Note to demonstrate the recom-

mended board layout options for this device. These techniques

include stitching capacitance and edge guarding.

Stitching Capacitance

Capacitance between the primary and secondary power

and ground planes is the most effective way to reduce high

frequency emissions from an isoPower device. Figure 2

shows how the inner layers of a PCB can create this stitching

capacitance by overlapping inner layer metal to create an

extremely low inductance capacitance. The green area

shows the active coupling area.

Edge Guarding

Providing guard rings laced together with vias on each layer of

the primary side reduces edge emissions from the PCB stack-up.

This addresses emissions due to differential currents flowing in

the ground planes from reaching the edge of the PCB where

they could radiate. Figure 4 shows the top layer guard ring and

the bottom layer ground fill as well as the regularly spaced vias

in the guard ring that creates a cage type structure to reflect

inter-plane emissions back into the PCB. Figure 5 shows the

top layer power fill along with its vias to the Layer 3 power

plane. This top layer power fill adds distributed capacitance

as well as shielding for the layer below.

HIGH VOLTAGE TESTING

This PCB is designed in line with 2500 V basic insulation

practices. High voltage testing beyond 2500 V is not recom-

mended. Appropriate care must be taken when using this

evaluation board at high voltages, and it should not be relied

on for safety functions because it has not been hi-pot tested

or certified for safety.