Output FET Disabling

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Figure 10. Start-up Circuit Timing Diagram

Figure 11 shows the expected waveform if the panel voltage is less than the battery voltage. The panel

Vmp for this example is 12V @ 3A and the battery voltage is at 25V. Figure 12 showcases the magnified

version of the battery current shown in Figure 11.

NOTE:

To highlight the boosting capability of the system and start-up circuit, the board has been re-

configured to run with a 24V battery for the experiments shown in Figure 11 and Figure 12.

Figure 11. Start-up V

Figure 12. Start-up Detail of Battery Current

9

Output FET Disabling

Q9 keep the topside output FET Q2 from turning on. The power will flow through the parallel diode D7

instead. This prevents the battery from discharging into the PV panels. Q2 can be disabled using the

microcontroller or a comparator (U12A) connected to the output current sensing: when current drops

below the threshold value, Q2 is disabled. The threshold is set to 1A by default.

8

AN-2121 SolarMagic™ SM3320-BATT-EV Charge Controller Reference

SNOSB76C – December 2010 – Revised May 2013

Design

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