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FM28V020-SGTR Arkusz danych(PDF) 8 Page - Cypress Semiconductor

Numer części FM28V020-SGTR
Szczegółowy opis  256Kbit Bytewide F-RAM Memory
Download  16 Pages
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM28V020-SGTR Arkusz danych(HTML) 8 Page - Cypress Semiconductor

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FM28V020 - 32Kx8 F-RAM
Document Number: 001-86204 Rev. *A
Page 8 of 16
Read Cycle AC Parameters (TA = -40 C to +85 C, CL = 30 pF, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tRC
Read Cycle Time
140
-
ns
tCE
Chip Enable Access Time
-
70
ns
tAA
Address Access Time
-
140
ns
tOH
Output Hold Time
20
-
ns
tAAP
Page Mode Address Access Time
-
40
ns
tOHP
Page Mode Output Hold Time
3
-
ns
tCA
Chip Enable Active Time
70
-
ns
tPC
Precharge Time
70
-
ns
tAS
Address Setup Time (to /CE low)
0
-
ns
tAH
Address Hold Time (/CE-controlled)
70
-
ns
tOE
Output Enable Access Time
-
20
ns
3
tHZ
Chip Enable to Output High-Z
-
10
ns
1
tOHZ
Output Enable High to Output High-Z
-
10
ns
1
Write Cycle AC Parameters (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tWC
Write Cycle Time
140
-
ns
tCA
Chip Enable Active Time
70
-
ns
tCW
Chip Enable to Write Enable High
70
-
ns
tPC
Precharge Time
70
-
ns
tPWC
Page Mode Write Enable Cycle Time
35
-
ns
tWP
Write Enable Pulse Width
18
-
ns
tAS
Address Setup Time (to /CE low)
0
-
ns
tAH
Address Hold Time (/CE-controlled)
70
-
ns
tASP
Page Mode Address Setup Time (to /WE low)
5
-
ns
tAHP
Page Mode Address Hold Time (to /WE low)
20
-
ns
tWLC
Write Enable Low to /CE High
25
-
ns
tWLA
Write Enable Low to A(14:3) Change
25
-
ns
tAWH
A(14:3) Change to Write Enable High
140
-
ns
tDS
Data Input Setup Time
15
-
ns
tDH
Data Input Hold Time
0
-
ns
tWZ
Write Enable Low to Output High Z
-
10
ns
1
tWX
Write Enable High to Output Driven
5
-
ns
1
tWS
Write Enable to /CE Low Setup Time
0
-
ns
1,2
tWH
Write Enable to /CE High Hold Time
0
-
ns
1,2
Notes
1
This parameter is characterized but not 100% tested.
2
The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs.
3
For VDD < 2.7V, tOE max is 25ns.
Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tVR
VDD Rise Time
50
-
s/V
1
tVF
VDD Fall Time
100
-
s/V
1
tPU
Power Up (VDD min) to First Access Time
250
-
s
tPD
Last Access to Power Down (VDD min)
0
-
s
Notes
1
Slope measured at any point on VDD waveform.


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