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AD7887AR-REEL7 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD7887AR-REEL7
Szczegółowy opis  2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP
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AD7887AR-REEL7 Arkusz danych(HTML) 5 Page - Analog Devices

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AD7887
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS1
Table 2.
Limit at TMIN, TMAX
(A, B Versions)
Parameter
4.75 V to 5.25 V
2.7 V to 3.6 V
Unit
Description
fSCLK2
2
2
MHz max
tCONVERT
14.5 × tSCLK
14.5 × tSCLK
tACQ
1.5 × tSCLK
1.5 × tSCLK
Throughput time = tCONVERT + tACQ = 16 tSCLK
t1
10
10
ns min
CS to SCLK setup time
t23
30
60
ns max
Delay from CS until DOUT three-state disabled
t33
75
100
ns max
Data access time after SCLK falling edge
t4
20
20
ns min
Data setup time prior to SCLK rising edge
t5
20
20
ns min
Data valid to SCLK hold time
t6
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK high pulse width
t7
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK low pulse width
t84
80
80
ns max
CS rising edge to DOUT high impedance
t9
5
5
μs typ
Power-up time from shutdown
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
200µA
IOH
1.6V
TO
OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications


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