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ADS5296 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS5296 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 104 page ADS5296 www.ti.com SBAS606A – MAY 2013 – REVISED MAY 2013 TIMING REQUIREMENTS (1) Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, sine-wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and LVDD = 1.7 V to 1.9 V, with decimation filters DISABLED. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tA Aperture delay 4 ns Aperture delay matching Between any two channels of the same device ±200 ps Between two devices at the same temperature and Variation of aperture delay ±1 ns AVDD supply tJ Aperture jitter Sample uncertainty 300 fs rms Time to valid data after coming out of standby 6 µs Wake-up time Time to valid data after coming out of global power- 100 µs down mode Input clock Interleaving disabled 12 cycles ADC latency(2) Input clock Interleaving enabled 24 cycles 10x SERIALIZATION tSU Data setup time Data valid to LCLKP zero-crossing 0.200 ns tH Data hold time LCLKP zero-crossing to data becoming invalid 0.160 ns Input clock rising edge crossover to output clock tPDI = (4 / 5) tPDI Clock propagation delay ns rising edge crossover × tS + tDELAY tDELAY Delay time 7.8 11.8 ns Between two devices at the same temperature and Variation of tDELAY ±0.8 ns LVDD supply Duty cycle of differential clock LVDS bit clock duty cycle 50 % (LCLKP – LCLKN) ACROSS ALL SERIALIZATION MODES Rise time measured from –100 mV to +100 mV, tFALL Data fall time 0.13 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tRISE Data rise time 0.13 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tCLKRISE Output clock rise time 0.13 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS Rise time measured from –100 mV to +100 mV, tCLKFALL Output clock fall time 0.13 ns 10 MSPS ≤ sampling frequency ≤ 100 MSPS (1) Timing parameters are ensured by design and characterization, but are not tested in production. (2) At higher frequencies, tPDI is greater than one clock period. Overall latency = ADC latency + 1. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS5296 |
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