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Zakładka z wyszukiwarką danych komponentów |
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DAC8811ICDRBR Arkusz danych(PDF) 9 Page - Texas Instruments |
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DAC8811ICDRBR Arkusz danych(HTML) 9 Page - Texas Instruments |
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9 / 21 page  www.ti.com t(CSS) t(DS) t(DH) t(CH) t(CL) t(CSH) SDI CLK CS D15 D14 D13 D12 D11 D10 D9 D8 D1 D0 APPLICATION INFORMATION Stability Circuit + − U2 GND U1 VREF VREF VDD VDD VOUT C1 IOUT RFB Positive Voltage Output Circuit DAC8811 SLAS411B – NOVEMBER 2004 – REVISED FEBRUARY 2007 THEORY OF OPERATION (continued) Figure 19. DAC8811 Timing Diagram Table 2. Control Logic Truth Table(1) CLK CS Serial Shift Register DAC Register X H No effect Latched ↑+ L Shift register data advanced one bit Latched X H No effect Latched X ↑+ Shift register data transferred to DAC register New data loaded from serial register (1) ↑+ Positive logic transition; X = Don't care Table 7.1. Serial Input Register Data Format, Data Loaded MSB First B15 B0 Bit (MSB) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB) Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 For a current-to-voltage design (see Figure 20), the DAC8811 current output (IOUT) and the connection with the inverting node of the op amp should be as short as possible and according to correct PCB layout design. For each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20. Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground and a -2.5 V input to the DAC8811 with an op amp. 9 Submit Documentation Feedback |
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