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ADW50007Z-0REEL7 Datasheet(Arkusz danych) 5 Page - Analog Devices

Numer części ADW50007Z-0REEL7
Szczegółowy opis  12-Bit High Bandwidth Multiplying DAC with Serial Interface
Pobierz  24 Pages
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Strona internetowa  http://www.analog.com
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Data Sheet
AD5452W
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, TA = full operating temperature range. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
V
DD = 2.5 V to 5.5 V
Unit
Conditions/Comments
f
SCLK
50
MHz max
Maximum clock frequency
t
1
20
ns min
SCLK cycle time
t
2
8
ns min
SCLK high time
t
3
8
ns min
SCLK low time
t
4
8
ns min
SYNC falling edge to SCLK active edge setup time
t
5
5
ns min
Data setup time
t
6
4.5
ns min
Data hold time
t
7
5
ns min
SYNC rising edge to SCLK active edge
t
8
30
ns min
Minimum SYNC high time
Update Rate
2.7
MSPS
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
Figure 2. Timing Diagram
SCLK
SYNC
SDIN
DB15
DB0
t7
t3
t2
t6
t5
t4
t8
t1




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