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DAC7563SDGSR Arkusz danych(PDF) 6 Page - Texas Instruments

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Numer części DAC7563SDGSR
Szczegółowy opis  DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/째C INTERNAL REFERENCE IN SMALL 3-MM3-MM SON
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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V
A
OUT
V
B
OUT
GND
LDAC
CLR
1
2
3
4
5
6
7
8
9
10
SYNC
SYNC
SCLK
SCLK
D
IN
D
IN
AV
DD
AV
DD
V
/V
REFIN
REFOUT
V
/V
REFIN
REFOUT
1
2
3
4
5
6
7
8
9
10
V
A
OUT
V
B
OUT
GND
LDAC
CLR
DGS
(Top View)
DSC
(Top View)
MSOP Package
SON Package
Thermal Pad
(1)
DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D – AUGUST 2010 – REVISED AUGUST 2012
www.ti.com
PIN CONFIGURATIONS
(1)
It is recommended to connect the thermal pad to the ground plane for better thermal dissipation.
Table 2. PIN DESCRIPTIONS
PIN
DESCRIPTION
NAME
NO.
AVDD
9
Power-supply input, 2.7 V to 5.5 V
Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale
(DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output
CLR
5
voltages accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If
CLR is activated during a write sequence, the write is aborted.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock
DIN
8
input. Schmitt-trigger logic input
GND
3
Ground reference point for all circuitry on the device
In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling
edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to
GND permanently or asserted and held low before sending commands to the device.
LDAC
4
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous
DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to
desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output
registers.
SCLK
7
Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input
Level-triggered control input (active-low). This input is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock
SYNC
6
edges. The DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd
clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the
DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input
VOUTA
1
Analog output voltage from DAC-A
VOUTB
2
Analog output voltage from DAC-B
VREFIN / VREFOUT
10
Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.
6
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Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563


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