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ADXL362BCCZ-R2 Arkusz danych(PDF) 39 Page - Analog Devices |
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ADXL362BCCZ-R2 Arkusz danych(HTML) 39 Page - Analog Devices |
39 / 44 page Data Sheet ADXL362 Rev. B | Page 39 of 44 FIFO data is output on a per datum basis. As each data item is read, the same amount of space is freed up in the stack. Again, this can lead to incomplete sample sets being present in the FIFO. For additional system level FIFO applications, refer to the AN-1025 Application Note, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers. INTERRUPTS Several of the built-in functions of the ADXL362 can trigger interrupts to alert the host processor of certain status conditions. This section describes the functionality of these interrupts. Interrupt Pins Interrupts can be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INTMAP1 and INTMAP2 registers, respectively. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are also placed in the high-Z state upon a reset. When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default so that when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INT_LOW bit in the appropriate INTMAPx register. The INT pins can be connected to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. Because multiple functions can be mapped to the same pin, the STATUS register can be used to determine which condition caused the interrupt to trigger. Clear interrupts in one of several ways, as follows: • Reading the STATUS register (Address 0x0B) clears activity and inactivity interrupts. • Reading from the data registers. Address 0x08 to Address 0x0A or Address 0x0E to Address 0x15 clears the data ready interrupt. • Reading enough data from the FIFO buffer so that interrupt conditions are no longer met clears the FIFO ready, FIFO watermark, and FIFO overrun interrupts. Both interrupt pins are push-pull low impedance pins with an output impedance of about 500 Ω (typical) and digital output specifications, as shown in Table 21. Both pins have bus keepers that hold them to a valid logic state when they are in a high impedance mode. To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured. Table 21. Interrupt Pin Digital Output Limit1 Parameter Test Conditions Min Max Unit Digital Output Low Level Output Voltage (VOL) IOL = 500 µA 0.2 × VDD I/O V High Level Output Voltage (VOH) IOH = −300 µA 0.8 × VDD I/O V Low Level Output Current (IOL) VOL = VOL, max 500 µA High Level Output Current (IOH) VOH = VOH, min −300 µA 1 Limits based on design, not production tested. |
Podobny numer części - ADXL362BCCZ-R2 |
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Podobny opis - ADXL362BCCZ-R2 |
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