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ADXL362BCCZ-R2 Arkusz danych(PDF) 17 Page - Analog Devices |
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ADXL362BCCZ-R2 Arkusz danych(HTML) 17 Page - Analog Devices |
17 / 44 page Data Sheet ADXL362 Rev. B | Page 17 of 44 Using the AWAKE Bit The AWAKE bit is a status bit that indicates whether the ADXL362 is awake or asleep. The device is awake when it has experienced an activity condition, and it is asleep when it has experienced an inactivity condition. The awake signal can be mapped to the INT1 or INT2 pin, allowing the pin to serve as a status output to connect or dis- connect power to downstream circuitry based on the awake status of the accelerometer. Used in conjunction with loop mode, this configuration implements a trivial, autonomous motion activated switch, as shown in Figure 43. If the turn-on time of downstream circuitry can be tolerated, this motion switch configuration can save significant system level power by eliminating the standby current consumption of the remainder of the application. This standby current can often exceed the full operating current of the ADXL362. FIFO The ADXL362 includes a deep 512-sample first in, first out (FIFO) buffer. The FIFO provides benefits primarily in two ways, as follows. System Level Power Savings Appropriate use of the FIFO enables system level power savings by enabling the host processor to sleep for extended periods of time while the accelerometer autonomously collects data. Alter- natively, using the FIFO to collect data can unburden the host while it tends to other tasks. Data Recording/Event Context The FIFO can be used in a triggered mode to record all data leading up to an activity detection event, thereby providing con- text for the event. In the case of a system that identifies impact events, for example, the accelerometer can keep the entire system off while it stores acceleration data in its FIFO and looks for an activity event. When the impact event occurs, data that was collected prior to the event is frozen in the FIFO. The accel- erometer can then wake the rest of the system and transfer this data to the host processor, thereby providing context for the impact event. Generally, the more context available, the more intelligent decisions a system can achieve, making a deep FIFO especially useful. The ADXL362 FIFO can store up to more than 13 seconds of data, providing a clear picture of events prior to an activity trigger. All FIFO modes of operation, as well as the structure of the FIFO and instructions for retrieving data from it, are described in further detail in the FIFO Modes section of this data sheet. COMMUNICATIONS SPI Instructions The digital interface of the ADXL362 is implemented with system level power savings in mind. The following features enhance power savings: • Burst reads and writes reduce the number of SPI communication cycles required to configure the part and retrieve data. • Concurrent operation of activity and inactivity detection enables “set it and forget it” operation. Loop mode further reduces communications power by enabling the clearing of interrupts without processor intervention. • The FIFO is implemented such that consecutive samples can be read continuously via a multibyte read of unlimited length; thus, one read FIFO instruction can clear the entire contents of the FIFO. In many other accelerometers, each read instruction retrieves a single sample only. In addition, the ADXL362 FIFO construction allows the use of direct memory access (DMA) to read the FIFO contents. Bus Keepers The ADXL362 includes bus keepers on all digital interface pins: MISO, MOSI, SCLK, CS, INT1, and INT2. Bus keepers are used to prevent tristate bus lines from floating when nothing is driving them, thus preventing through current in any gate inputs that are on the bus. MSB Registers Acceleration and temperature measurements are converted to 12-bit values and transmitted via SPI using two registers per measurement. To read a full sample set of 3-axis acceleration data, six registers must be read. Many applications do not require the accuracy that 12-bit data provides and prefer, instead, to save system level power. The MSB registers XDATA, YDATA, and ZDATA enable this tradeoff. These registers contain the eight MSBs of the x-, y-, and z-axis acceleration data; reading them effectively provides 8-bit accel- eration values. Importantly, only three (consecutive) registers must be read to retrieve a full data set, significantly reducing the time during which the SPI bus is active and drawing current. 12-bit and 8-bit data are available simultaneously so that both data formats can be used in a single application, depending on the needs of the application at a given time. For example, the pro- cessor can read 12-bit data when higher resolution is required, and switch to 8-bit data (simply by reading a different set of registers) when application requirements change. |
Podobny numer części - ADXL362BCCZ-R2 |
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Podobny opis - ADXL362BCCZ-R2 |
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