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ADXL362BCCZ-R2 Arkusz danych(PDF) 22 Page - Analog Devices |
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ADXL362BCCZ-R2 Arkusz danych(HTML) 22 Page - Analog Devices |
22 / 44 page ADXL362 Data Sheet Rev. B | Page 22 of 44 Table 10. SPI Timing (TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V) Limit1, 2 Parameter Min Max Unit Description fCLK 1 MHz Clock Frequency CSS 100 ns CS Setup Time tCSH 100 ns CS Hold Time tCSD 10 ns CS Disable Time tSU 50 ns Data Setup Time tHD 50 ns Data Hold Time tR 0 100 ns SCLK Rise Time tF 0 100 ns SCLK Fall Time tHIGH 100 ns Clock High Time tLOW 100 ns Clock Low Time tCLD 100 ns Clock Delay Time tCLE 100 ns Clock Enable Time tV 0 ns Output Valid from Clock Low tHO 0 200 ns Output Hold Time tDIS 0 200 ns Output Disable Time 1 Limits based on design targets; not production tested. 2 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9. |
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