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ADG1212YRUZ-REEL Arkusz danych(PDF) 7 Page - Analog Devices |
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ADG1212YRUZ-REEL Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 16 page Data Sheet ADG1211/ADG1212/ADG1213 Rev. B | Page 7 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TOP VIEW 1 2 3 4 5 6 7 8 ADG1211/ ADG1212/ ADG1213 NC = NO CONNECT 16 15 14 13 12 11 10 9 D1 S1 VSS D4 S4 GND IN1 D2 S2 VDD D3 IN4 IN3 S3 NC IN2 Figure 2. TSSOP Pin Configuration PIN 1 INDICATOR NC = NO CONNECT NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 1 S1 2 VSS 3 GND 4 S4 11 VDD 12 S2 10 NC 9 S3 TOP VIEW (Not to Scale) ADG1211/ADG1212/ADG1213 Figure 3. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description TSSOP LFCSP 1 15 IN1 Logic Control Input. 2 16 D1 Drain Terminal. Can be an input or output. 3 1 S1 Source Terminal. Can be an input or output. 4 2 VSS Most Negative Power Supply Potential. 5 3 GND Ground (0 V) Reference. 6 4 S4 Source Terminal. Can be an input or output. 7 5 D4 Drain Terminal. Can be an input or output. 8 6 IN4 Logic Control Input. 9 7 IN3 Logic Control Input. 10 8 D3 Drain Terminal. Can be an input or output. 11 9 S3 Source Terminal. Can be an input or output. 12 10 NC No Internal Connection. 13 11 VDD Most Positive Power Supply Potential. 14 12 S2 Source Terminal. Can be an input or output. 15 13 D2 Drain Terminal. Can be an input or output. 16 14 IN2 Logic Control Input. |
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