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4TPC150M Arkusz danych(PDF) 11 Page - Texas Instruments

Numer części 4TPC150M
Szczegółowy opis  DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
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4TPC150M Arkusz danych(HTML) 11 Page - Texas Instruments

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TPS70445, TPS70448
TPS70451, TPS70458
TPS70402
www.ti.com
SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010
Detailed Description
The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable
functions. These devices provide fast transient response and high accuracy with small output capacitors, while
drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good
(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features
provide a complete power solution.
The TPS704xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even
with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly
proportional to the load current through the regulator (IB = IC/b). The TPS704xx uses a PMOS transistor to pass
current; because the gate of the PMOS is voltage-driven, operating current is low and stable over the full load
range.
Pin Functions
Enable (EN1, EN2)
The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal,
the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled.
Power-Good (PG1, PG2)
The PG terminals are open drain, active high output terminals that indicate the status of each respective
regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When VOUT2
reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance
state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its
regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor.
Manual Reset Pin
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR
(RESET) occurs. The terminal has a 6-mA pull-up current to VIN1; however, it is recommended that the pin be
pulled high to VIN1 when it is not used.
Sense (VSENSE1, VSENSE2)
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection
should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth
amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential
to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between
sense terminals and VOUT terminals to filter noise is not recommended because these networks can cause the
regulators to oscillate.
Copyright © 2000–2010, Texas Instruments Incorporated
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