Circuit Note

CN-0227

Rev. A | Page 3 of 5

0.1µF

GAIN

0.1µF

0.1µF

0.1µF

XFMR

1:1 Z

ECT1-1-13M

ANALOG INPUT

INPUT

Z = 50Ω

ADC

INTERNAL

INPUT Z

0.1µF

0.1µF

FILTER

Figure 5. Generalized Differential Amplifier/ADC Interface with Low-Pass Filter

Filter and Interface Design Procedure

In this section, a general approach to the design of the amplifier/

ADC interface with filter is presented. To achieve optimum

performance (bandwidth, SNR, and SFDR), there are certain

design constraints placed on the general circuit by the amplifier

and the ADC:

1.

The amplifier should see the correct dc load recommended

by the data sheet for optimum performance.

2.

The correct amount of series resistance must be used between

the amplifier and the load presented by the filter. This is to

prevent undesired peaking in the pass band.

3.

The input to the ADC should be reduced by an external

parallel resistor, and the correct series resistance should be

used to isolate the ADC from the filter. This series resistor

also reduces peaking.

The generalized circuit shown in Figure 5 applies to most high

speed differential amplifier/ADC interfaces and will be used as

a basis for the discussion. This design approach will tend to

minimize the insertion loss of the filter by taking advantage of

the relatively high input impedance of most high speed ADCs

and the relatively low impedance of the driving source (amplifier).

The basic design process is as follows:

1.

and 400 Ω.

2.

recommendations, typically between 5 Ω and 36 Ω.

3.

Calculate the filter load impedance using:

4.

than 10 Ω if the amplifier differential output impedance is

impedance of the amplifier is 12 Ω or less.

5.

is optimum for the particular differential amplifier chosen

using the equation:

6.

Calculate the filter source resistance:

7.

Using a filter design program or tables design the filter

type of filter, bandwidth, and order. Use a bandwidth that

is about 40% higher than one-half the sampling rate to

ensure flatness in the frequency span between dc and fs/2.

8.

from the final shunt capacitor value generated by the

differential shunt capacitor. The final common-mode

shunt capacitance is

After running these preliminary calculations, the circuit should

be given a quick review for the following items.

1.

2.

that the filter is within the limits of most filter tables and

design programs.

3.

sensitivity to parasitic capacitance and component

variations.

4.

several nH.