Micrel, Inc.

SM802149

March 1, 2013

3

Revision 1.1

hbwhelp@micrel.com or (408) 955-1690

Pin Description

Pin Number

Pin Name

Pin Type

Pin Level

Pin Function

25, 26

28, 29

32, 33

35, 36

/Q1, Q1

/Q2, Q2

/Q3, Q3

/Q4, Q4

O, (DIF)

LVDS

Differential Clock Outputs from Bank 1

312.50MHz/156.25MHz

41, 42

1, 2

4, 5

7, 8

/Q5, Q5

/Q6, Q6

/Q7, Q7

/Q8, Q8

O, (DIF)

LVDS

Differential Clock Outputs from Bank 2

156.25MHz/78.125MHz

31, 37, 38

VDDO1

PWR

Power Supply for the Outputs on Bank 1

43, 44, 16

VDDO2

PWR

Power Supply for the Outputs on Bank 2

24, 39

VSSO1

PWR

Power Supply Ground for the Outputs on Bank 1

3, 6, 40

VSSO2

PWR

Power Supply Ground for the Outputs on Bank 2

23

GND

I, (SE)

This pin is not a Power Supply Ground, but MUST be tied to VSS

10

XTAL_SEL

I, (SE)

LVCMOS

Selects PLL Input Reference Source

0 = REF_IN

1 = XTAL

45k

Ω pull-up

11, 20, 27, 30, 34

TEST

Factory Test Pins. Do not connect anything to these pins.

12, 13

VDD

PWR

Core Power Supply

21

VSS

(Exposed Pad)

PWR

Core Power Supply Ground. The exposed pad must be connected

to the VSS ground plane.

9

PLL_BYPASS

I, (SE)

LVCMOS

PLL Bypass is a dual-function input. Normal operation selects

output source.

0 = Normal PLL operation

1 = Output from crystal oscillator

45k

Ω pull-down

18

XTAL_IN

I, (SE)

10pF crystal

Crystal Reference Input. No load caps needed.

See Figure 5.

19

XTAL_OUT

O, (SE)

10pF crystal

Crystal Reference Output. No load caps needed.

See Figure 5.

17

REF_IN

I, (SE)

LVCMOS

26.04166MHz Reference Clock Input

14

FSEL

I, (SE)

LVCMOS

Frequency Select.

1 = 312.5MHz/156.25 MHz

0 = 156.25MHz/78.125MHz.

Internal 45kΩ pull-up

15

OE1

I, (SE)

LVCMOS

Output Enable. Q1

−Q4 disables to tri-state.

0 = Disabled

1 = Enabled

45k

Ω pull-up

22

OE2

I, (SE)

LVCMOS

Output Enable. Q5

−Q8 disables to tri-state.

0 = Disabled

1 = Enabled

45k

Ω pull-up