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AD5641AKSZ-500RL7 Arkusz danych(PDF) 3 Page - Analog Devices

Numer części AD5641AKSZ-500RL7
Szczegółowy opis  SPI Interface in LFCSP and SC70
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD5641AKSZ-500RL7 Arkusz danych(HTML) 3 Page - Analog Devices

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Data Sheet
AD5641
Rev. D | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; −40°C < TA < +125°C; typical at +25°C; all specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
14
14
Bits
Relative Accuracy1
±16
±4
LSB
Differential Nonlinearity1
±1
±1
LSB
Guaranteed monotonic by design
Zero-Code Error
0.5
10
0.5
10
mV
All 0s loaded to DAC register
Offset Error
±0.63
±10
±0.63
±10
mV
Full-Scale Error
±0.5
±0.5
mV
All 1s loaded to DAC register
Gain Error
±0.004
±0.037
±0.004
±0.037
% of FSR
Zero-Code Error Drift
5.0
5.0
µV/°C
Gain Temperature Coefficient
2.0
2.0
ppm of
FSR/°C
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
VDD
0
VDD
V
Output Voltage Settling Time
6
10
6
10
µs
Code ¼ scale to ¾ scale, to ±1 LSB
Slew Rate
0.5
0.5
V/µs
Capacitive Load Stability
470
470
pF
RL = ∞
1000
1000
pF
RL = 2 kΩ
Output Noise Spectral Density
120
120
nV/√Hz
DAC code = midscale, 1 kHz
Noise
2
2
µV
DAC code = midscale, 0.1 Hz to
10 Hz bandwidth
Digital-to-Analog Glitch
Impulse
5
5
nV-s
1 LSB change around major carry
Digital Feedthrough
0.2
0.2
nV-s
DC Output Impedance
0.5
0.5
Short-Circuit Current
15
15
mA
VDD = 3 V/5 V
LOGIC INPUTS
Input Current3
±2
±2
µA
VINL, Input Low Voltage
0.8
0.8
V
VDD = 4.5 V to 5.5 V
0.6
0.6
V
VDD = 2.7 V to 3.6 V
VINH, Input High Voltage
1.8
1.8
V
VDD = 4.5 V to 5.5 V
1.4
1.4
V
VDD = 2.7 V to 3.6 V
Pin Capacitance
3
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
All digital inputs at 0 V or VDD
IDD (Normal Mode)
DAC active and excluding load current
VDD = 4.5 V to 5.5 V
75
100
75
100
µA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
60
90
60
90
µA
VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
0.5
0.5
µA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
0.2
0.2
µA
VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD
96
96
%
ILOAD = 2 mA and VDD = ±5 V, full-scale
loaded
1
Linearity calculated using a reduced code range (Code 256 to Code 16,128).
2
Guaranteed by design and characterization, not production tested.
3
Total current flowing into all pins.


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