ADN2890

Rev. 0 | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

5

6

7

8

16

15

14

13

TOP VIEW

(Not To Scale)

DRVCC

12

OUTN

10

DRVEE

9

OUTP

11

ADN2890

Figure 2. Pin Configuration

Note: There is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias.

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

I/O

Description

1

AVCC

Power

Analog Power

2

PIN

Input

Differential Data Input

3

NIN

Input

Differential Data Input

4

AVEE

Power

Analog Ground

5

THRADJ

Input

LOS Threshold Adjust Resistor

6

CAZ1

Offset Correction Loop Capacitor

7

CAZ2

Offset Correction Loop Capacitor

8

LOS

Output

LOS Detector Output

9

DRVEE

Power

Output Buffer Ground

10

OUTN

Output

Differential Data Output

11

OUTP

Output

Differential Data Output

12

DRVCC

Power

Output Buffer Power

13

SQUELCH

Input

Disable Outputs

14

RSSI_OUT

Output

Average Current Output

15

PD_VCC

Power

Power Input for RSSI Measurement

16

PD_CATHODE

Output

Photodiode Bias Voltage

Exposed Pad

Pad

Power

Connect to Ground