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ADSP-21369KBPZ-2A Arkusz danych(PDF) 1 Page - Analog Devices

Numer części ADSP-21369KBPZ-2A
Szczegółowy opis  SHARC Processors
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Strona internetowa  http://www.analog.com
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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC Processors
ADSP-21367/ADSP-21368/ADSP-21369
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 58.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
Figure 1. Functional Block Diagram
Internal Memory I/F
Block 0
RAM/ROM
B0D
64-BIT
Instruction
Cache
5 stage
Sequencer
PEx
PEy
PMD
64-BIT
IOD0 32-BIT
EPD BUS 32-BIT
Core Bus
Cross Bar
DAI Routing/Pins
S/PDIF
Tx/Rx
PCG
A-D
DPI Routing/Pins
SPI/B
UART
1-0
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
AMI
SDRAM
EP
External Port Pin MUX
TIMER
2-0
SPORT
7-0
ASRC
3-0
PWM
3-0
DAG1/2
Timer
IDP/
PDAP
7-0
TWI
IOD0 BUS
MTM
PCG
C-D
PERIPHERAL BUS
32-BIT
CORE
FLAGS
FLAGx/IRQx/
TMREXP
JTAG
Internal Memory
DMD
64-BIT
PMD 64-BIT
DMD 64-BIT
CORE
FLAGS
IOD1
32-BIT
PERIPHERAL BUS
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DPI Peripherals
DAI Peripherals
Peripherals
External
Port
SIMD Core
S


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