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ADC081S051CIMFX Arkusz danych(PDF) 2 Page - Texas Instruments |
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ADC081S051CIMFX Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 26 page T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CS SDATA CONTROL LOGIC VIN ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Block Diagram PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 CS Chip select. On the falling edge of CS, a conversion process begins. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to 1 VA GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 2 GND The ground return for the supply and signals. PAD GND For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC081S051 |
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