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AD1871YRSZ Arkusz danych(PDF) 17 Page - Analog Devices |
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AD1871YRSZ Arkusz danych(HTML) 17 Page - Analog Devices |
17 / 28 page REV. 0 AD1871 –17– Digital Decimating Filters The filtering and decimation of the AD1871’s modulator data stream is implemented in an embedded DSP engine. The first stage of filtering is the sinc filtering, which has selectable deci- mation (selected by the modulator clock control bit (AMC, see Modulator section). The default decimation in the sinc stage provides a sample rate reduction of 16; this corresponds with a MODCLK rate of 128 ¥ fS. The alternate setting of the AMC Bit gives a sinc decimation factor of 8 that corresponds with a MODCLK rate of 64 ¥ fS. The output of the sinc decimator stage is at a rate of 8 ¥ fS. The filter engine implements two half-band FIR filter sections and a sinc compensation stage that together give a further decimation factor of 8. Please refer to TPCs 1 through 4 for details on the responses of the sinc and FIR filter sections. TPC 5 gives the composite response of the sinc and FIR filters. High-Pass Filter The AD1871 features an optional high-pass filter section that provides the ability of rejecting dc from the output data stream. The high-pass filter is enabled by setting Bit 8 (HPE) of Control Register I to 1. Please refer to TPC 7 and TPC 8 for details of the high-pass filter characteristics. ADC Coding The ADC’s output data stream is in a two’s complement encoded format. The word width can be selected from 16 bits, 20 bits, or 24 bits (see Table VI and Table VII). The coding scheme is detailed in Table I. Table I. ADC Coding Code Level 011111.......1111 +Full Scale 000000........0000 0 (Ref Level) 100000........0001 –Full Scale Analog Input Section The analog input section comprises a differential PGA stage. It can also be configured for single-ended inputs, allowing two such inputs to be selected via a multiplex switch. The PGA has five gain settings (see Table V) ranging from 0 dB to 12 dB in 3 dB steps. In Differential Mode, the VINxP and VINxN input pins are connected to a pair of inverting amplifiers whose outputs are connected to the CAPxN and CAPxP pins, respectively. (See Figure 10.) CAPxN CAPxP VCM VINxP VINxN VCM Figure 10. Differential Analog Input In Single-Ended Mode, either VINxP or VINxN can be selected as the input. The pair of input inverting amplifiers is reconfig- ured as a single-ended-to-differential conversion stage. Again the outputs of the differential section are connected to Pins CAPxP and CAPxN (see Figure 11). CAPxN CAPxP VCM VINxP VINxN VCM Figure 11. Single-Ended Analog Input The analog input section is enabled (powered ON) by default on reset. If it is required to bypass the analog input section by using the modulator input pins (CAPxP and CAPxN) directly, then the analog input section must be powered down by setting Bits MER and MEL in Control Register III. Serial Data Interface The AD1871’s serial data interface consists of three pins (LRCLK, BCLK, and SDATA). LRCLK is the framing sig- nal for left and right channel samples and its frequency is equal to the sampling frequency (fS). BCLK is the serial clock used to clock the data samples from the AD1871 and its fre- quency is equal to 64 ¥ fS (giving 32 BCLK periods for each of the left and right channels). SDATA outputs the left and right channel sample data coincident with the falling edge of BCLK. The serial data interface supports all the popular audio interface standards, such as I 2S, left-justified (LJ), and right-justified (RJ), as well as the serial interfaces of modern DSPs. The Interface Mode is selected by programming the Bits DF1–DF0 of Control Register II (see Tables VI and VIII). The data sample width can be selected from 16, 20, or 24 bits by programming Bits WW1–WW0 of Control Register II (see Tables VI and VII). |
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