Data Sheet

AD9639

Rev. B | Page 5 of 36

DIGITAL SPECIFICATIONS

otherwise noted.

Table 3.

AD9639BCPZ-170

AD9639BCPZ-210

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Full

LVPECL/LVDS/CMOS

LVPECL/LVDS/CMOS

Differential Input Voltage

Full

0.2

6

0.2

6

V p-p

Input Voltage Range

Full

AVDD −

0.3

AVDD +

1.6

AVDD −

0.3

AVDD +

1.6

Internal Common-Mode Bias

Full

1.2

1.2

V

Input Common-Mode Voltage

Full

1.1

AVDD

1.1

AVDD

V

Full

1.2

3.6

1.2

3.6

V

Full

0

0.8

0

0.8

V

Full

−10

+10

−10

+10

µA

Full

−10

+10

−10

+10

µA

Differential Input Resistance

25°C

16

20

24

16

20

24

kΩ

Input Capacitance

25°C

4

4

pF

LOGIC INPUTS (PDWN, CSB, SDI/SDIO,

SCLK, RESET, PGMx)2

Logic 1 Voltage

Full

0.8 ×

AVDD

0.8 ×

AVDD

V

Logic 0 Voltage

Full

0.2 ×

AVDD

0.2 ×

AVDD

V

Logic 1 Input Current (CSB)

Full

0

0

µA

Logic 0 Input Current (CSB)

Full

−60

−60

µA

Logic 1 Input Current

(PDWN, SDI/SDIO, SCLK,

RESET, PGMx)

Full

55

55

µA

Logic 0 Input Current

(PDWN, SDI/SDIO, SCLK,

RESET, PGMx)

Full

0

0

µA

Input Resistance

25°C

30

30

kΩ

Input Capacitance

25°C

4

4

pF

LOGIC OUTPUT (SDO)

Logic 1 Voltage

Full

1.2

AVDD +

0.3

1.2

AVDD +

0.3

V

Logic 0 Voltage

Full

0

0.3

0

0.3

V

DIGITAL OUTPUTS (DOUT + x, DOUT − x)

Logic Compliance

CML

CML

Differential Output Voltage

Full

0.8

0.8

V

Common-Mode Voltage

Full

DRVDD/2

DRVDD/2

V

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2

Specified for 13 SDI/SDIO pins on the same SPI bus.