AD9822

Rev. B | Page 10 of 20

PIXEL N (R, G, B)

PIXEL (N + 1)

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1)

R (N)

R (N)

G (N)

G (N)

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

Figure 5. 3-Channel SHA Mode Timing

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

PIXEL N

HIGH BYTE

LOW BYTE

LOW BYTE

HIGH BYTE

HIGH BYTE

LOW BYTE

PIXEL (N – 4)

PIXEL (N – 4)

PIXEL (N – 3)

PIXEL (N – 3)

PIXEL (N – 2)

PIXEL (N – 2)

Figure 6. 1-Channel SHA Mode Timing