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AD9773BSV Arkusz danych(PDF) 1 Page - Analog Devices |
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AD9773BSV Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 60 page 12-Bit, 160 MSPS, 2×/4×/ 8× Interpolating Dual TxDAC D/A Converter AD9773 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES 12-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment fS/2, fS/4, fS/8 digital quadrature modulation capability Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI port Excellent ac performance SFDR −69 dBc @ 2 MHz to 35 MHz WCDMA ACPR −69 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thin quad flat package, exposed pad (TQFP_EP) APPLICATIONS Communications Analog quadrature modulation architecture 3G, multicarrier GSM, TDMA, CDMA systems Broadband wireless, point-to-point microwave radios Instrumentation/ATE FUNCTIONAL BLOCK DIAGRAM 16 16 16 /2 16 16 16 16 16 /2 /2 /2 AD9773 DATA ASSEMBLER I LATCH Q LATCH MUX CONTROL SPI INTERFACE AND CONTROL REGISTERS HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY * I AND Q NONINTERLEAVED OR INTERLEAVED DATA 12 12 CLOCK OUT WRITE SELECT HALF- BAND FILTER1* FILTER BYPASS MUX IMAGE REJECTION/ DUAL DAC MODE BYPASS MUX I/Q DAC GAIN/OFFSET REGISTERS HALF- BAND FILTER2* HALF- BAND FILTER3* COS IDAC IDAC GAIN DAC DIFFERENTIAL CLK OFFSET DAC COS IOUT PRESCALER PLL CLOCK MULTIPLIER AND CLOCK DIVIDER PHASE DETECTOR AND VCO SIN SIN fDAC/2, 4, 8 ( fDAC) Figure 1. |
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