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AD9786BSVRL Arkusz danych(PDF) 1 Page - Analog Devices |
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AD9786BSVRL Arkusz danych(HTML) 1 Page - Analog Devices |
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1 / 56 page  16-Bit, 200 MSPS/500 MSPS TxDAC+® with 2×/4×/8× Interpolation and Signal Processing AD9786 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.3 LSB INL = ±0.6 LSB Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes Single- or dual-channel signal processing Selectable image rejection Hilbert transform Flexible calibration engine Direct IF transmission features Serial control interface Versatile clock and data interface 3.3 V-compatible digital interface On-chip 1.2 V reference 80-lead, thermally enhanced, TQFP_EP package APPLICATIONS Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA, IS136, TETRA Instrumentation RF signal generators, arbitrary waveform generators HDTV transmitters Broadband wireless systems Digital radio links Satellite systems PRODUCT HIGHLIGHTS 1. 16-bit, high speed, interpolating TxDAC+. 2. 2×/4×/8× user-selectable interpolating filter. The filter eases data rate and output signal reconstruction filter requirements. 3. 200 MSPS input data rate. 4. Ultra high speed, 500 MSPS DAC conversion rate. 5. Flexible clock with single-ended or differential input. CMOS, 1 V p-p sine wave, and LVPECL capability. 6. Complete CMOS DAC function. It operates from a 3.1 V to 3.5 V single analog (AVDD) supply, 2.5 V digital supply, and a 3.3 V digital (DRVDD) supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 7. On-chip voltage reference. The AD9786 includes a 1.20 V temperature-compensated band gap voltage reference. 8. Multichip synchronization. Multiple AD9786 DACs can be synchronized to a single master AD9786 to ease timing design requirements and optimize image reject transmit performance. FUNCTIONAL BLOCK DIAGRAM 16-BIT DAC ZERO STUFF HILBERT Δt 0 90 0 90 2× 2× 2× LATCH Q fDAC/2 fDAC/4 fDAC/8 ×1 CLOCK DISTRIBUTION AND CONTROL CLK+ CLK– DATACLK P2B[15:0] P1B[15:0] FSADJ REFIO IOUTA IOUTB SDIO SDO CSB SCLK RESET 0 90 2× 2× 2× LATCH I Figure 1. |
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