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ADN4667ARUZ Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADN4667ARUZ
Szczegółowy opis  3 V LVDS Quad CMOS Differential Line Driver
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ADN4667
Data Sheet
Rev. B | Page 4 of 16
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. All typical values are given
for VCC = +3.3 V, TA = +25°C.
Table 2.
Parameter2
Min
Typ
Max
Unit
Conditions/Comments3, 4
Differential Propagation Delay, High to Low, t
PHLD
0.5
0.9
1.7
ns
See Figure 3 and Figure 4
Differential Propagation Delay, Low to High, t
PLHD
0.5
1.2
1.7
ns
See Figure 3 and Figure 4
Differential Pulse Skew |t
PHLD − tPLHD|, tSKD1
5
0
0.3
0.4
ns
See Figure 3 and Figure 4
Channel-to-Channel Skew, t
SKD2
6
0
0.4
0.5
ns
See Figure 3 and Figure 4
Differential Part-to-Part Skew, t
SKD3
7
0
1.0
ns
See Figure 3 and Figure 4
Differential Part-to-Part Skew, t
SKD4
8
0
1.2
ns
See Figure 3 and Figure 4
Rise Time, t
r
0.5
1.5
ns
See Figure 3 and Figure 4
Fall Time, t
f
0.5
1.5
ns
See Figure 3 and Figure 4
Disable Time High to Inactive, t
PHZ
2
5
ns
See Figure 5 and Figure 6
Disable Time Low to Inactive, t
PLZ
2
5
ns
See Figure 5 and Figure 6
Enable Time Inactive to High, t
PZH
3
7
ns
See Figure 5 and Figure 6
Enable Time Inactive to Low, t
PZL
3
7
ns
See Figure 5 and Figure 6
Maximum Operating Frequency, f
MAX
9
200
250
MHz
See Figure 5 and Figure 6
1 C
L includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests unless otherwise specified: f = 50 MHz, Z
O = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5 t
SKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 t
SKD2 is the differential channel-to-channel skew of any event on the same device.
7 t
SKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 t
SKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
9 f
MAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
Test Circuits and Timing Diagrams
Figure 2. Test Circuit for Driver VOD and VOS
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
RL/2
RL/2
DIN
DOUT+
DOUT–
VCC
VOS
VOD
DRIVER IS ENABLED
V
V
CL
CL
DIN
DOUT+
DOUT–
DRIVER IS
ENABLED
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
SIGNAL
GENERATOR
VCC
50


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