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ADP5589ACPZ-00-R7 Arkusz danych(PDF) 8 Page - Analog Devices |
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ADP5589ACPZ-00-R7 Arkusz danych(HTML) 8 Page - Analog Devices |
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8 / 52 page  ADP5589 Data Sheet Rev. B | Page 8 of 52 DEVICE ENABLE When sufficient voltage is applied to VDD and the RST pin is driven with a logic high level, the ADP5589 starts up in standby mode with all settings at default. The user can configure the device via the I2C interface. When the RST pin is low, the ADP5589 enters a reset state and all settings return to default. The RST pin features a debounce filter. DEVICE OVERVIEW The ADP5589 contains 19 multiconfigurable input/output pins. Each pin can be programmed to enable the device to carry out its various functions, as follows: • Keypad matrix decoding (11-column by 8-row matrix maximum). • General-purpose I/O expansion (up to 19 inputs/outputs). • PWM generation. • Clock division of externally supplied source. • Dual logic function building blocks (up to three inputs, one output). • Two reset generators. All 19 input/output pins have an I/O structure, as shown in Figure 6. I/O VDD 100kΩ I/O DRIVE DEBOUNCE 300kΩ 300kΩ Figure 6. I/O Structure Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or pulled down with a 300 kΩ resistor. For logic output drive, each I/O has a 5 mA PMOS source and a 10 mA NMOS sink for push-pull type output. For open-drain output situations, the 5 mA PMOS source is not enabled. For logic input applications, each I/O can be sampled directly or, alternatively, sampled through a debounce filter. The I/O structure shown in Figure 6 allows for all GPI and GPO functions, as well as PWM and clock divide functions. For key matrix scan and decode, the scanning circuit uses the 100 kΩ or 300 kΩ resistor for pulling up keypad row pins and the 10 mA NMOS sinks for grounding keypad column pins (see the Key Scan Control section for details about key decoding). Configuration of the device is carried out by programming an array of internal registers via the I2C interface. Feedback of device status and pending interrupts can be flagged to an external processor via the INT pin. The ADP5589 is offered with three feature sets. Table 5 lists the options that are available for each model of the ADP5589. Table 5. Available Options Models Description ADP5589ACPZ-00-R7 ADP5589ACBZ-00-R7 All GPIOs pulled up (default option) ADP5589ACPZ-01-R7 ADP5589ACBZ-01-R7 Reset pass-through1 ADP5589ACPZ-02-R7 ADP5589ACBZ-02-R7 Pull-down on special function pins2 1 Reset pass-through implies that the RESET1 output (R4) follows the logic level of the reset input pin, RST, after the oscillator has been enabled. 2 Special function pins are defined as R0 (Row 0), R3 (Row 3), R4 (Row 4), C4 (Column 4), C6 (Column 6), and C9 (Column 9). |
Podobny numer części - ADP5589ACPZ-00-R7 |
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Podobny opis - ADP5589ACPZ-00-R7 |
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