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ADSP-21061KSZ-160 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części ADSP-21061KSZ-160
Szczegółowy opis  Commercial Grade SHARC DSP Microcomputer
Download  52 Pages
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Strona internetowa  http://www.analog.com
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ADSP-21061KSZ-160 Arkusz danych(HTML) 1 Page - Analog Devices

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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages. For more information, see Ordering
Guide on Page 52.
Figure 1. Functional Block Diagram
MULT
BARREL
SERIAL PORTS
(2)
4
6
6
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
I/O PROCESSOR
TIMER
INSTRUCTION
CACHE
ADDR
DATA
DATA
ADDR
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
48
32
24
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
32
48
40/32
CORE PROCESSOR
PROGRAM
SEQUENCER
8
4
32
DAG2
8
4
24
32
48-BIT
PM ADDRESS BUS
DATA
CONTROLLER
DMA
DATA
REGISTER
FILE
16
40-BIT
S
ALU
SHIFTER


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