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ADV7123KSTZ50 Arkusz danych(PDF) 3 Page - Analog Devices |
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ADV7123KSTZ50 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 24 page ADV7123 Rev. D | Page 3 of 24 SPECIFICATIONS 5 V SPECIFICATIONS VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C. Table 1. Parameter Min Typ Max Unit Test Conditions1 STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance, CIN 10 pF ANALOG OUTPUTS Output Current 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA RGB DAC, SYNC = low DAC-to-DAC Matching 1.0 5 % Output Compliance Range, VOC 0 1.4 V Output Impedance, ROUT 100 kΩ Output Capacitance, COUT 10 pF IOUT = 0 mA Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V Gain Error2 −5.0 +5.0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE, EXTERNAL AND INTERNAL Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current3 3.4 9 mA fCLK = 50 MHz 10.5 15 mA fCLK = 140 MHz 18 25 mA fCLK = 240 MHz Analog Supply Current 67 72 mA RSET = 560 Ω 8 mA RSET = 4933 Ω Standby Supply Current4 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz. 2 Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896. 3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 4 These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range. |
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