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74AC273 Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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74AC273 Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 12 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC273, 74ACT273 Rev. 1.6.0 2 Connection Diagram Pin Description Logic Symbols IEEE/IEC Mode Select-Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs Operating Mode Inputs Outputs MR CP Dn Qn Reset (Clear) L X X L Load ‘1' H H H Load ‘0' H L L |
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