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AD9523BCPZ Arkusz danych(PDF) 10 Page - Analog Devices

Numer części AD9523BCPZ
Szczegółowy opis  Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9523BCPZ Arkusz danych(HTML) 10 Page - Analog Devices

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AD9523
Data Sheet
Rev. C | Page 10 of 60
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Current
Input Logic 1
1
µA
Input Logic 0
1
µA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
8
ns
Pulse Width Low, tLOW
12
ns
SDIO to SCLK Setup, tDS
3.3
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
14
ns
CS to SCLK Setup, tS
10
ns
CS to SCLK Setup and Hold, tS, tC
0
ns
CS Minimum Pulse Width High, tPWH
6
ns
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage
0.7 × VDD
V
Input Logic 0 Voltage
0.3 × VDD
V
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
−10
+10
µA
Hysteresis of Schmitt Trigger Inputs
0.015 × VDD
V
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSPIKE
50
ns
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
0.4
V
Output Fall Time from VIHMIN to VILMAX with
a Bus Capacitance from 10 pF to 400 pF
20 + 0.1 CB1
250
ns
TIMING
Note that all I2C timing values are referred to
VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)
Clock Rate (SCL, fI2C)
400
kHz
Bus Free Time Between a Stop and Start
Condition, tIDLE
1.3
µs
Setup Time for a Repeated Start Condition, tSET;
STR
0.6
µs
Hold Time (Repeated) Start Condition, tHLD;STR
0.6
µs
After this period, the first clock pulse is
generated
Setup Time for Stop Condition, tSET;STP
0.6
µs
Low Period of the SCL Clock, tLOW
1.3
µs
High Period of the SCL Clock, tHIGH
0.6
µs
SCL, SDA Rise Time, tRISE
20 + 0.1 CB1
300
ns


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