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AD9739BBCZ Arkusz danych(PDF) 2 Page - Analog Devices

Numer części AD9739BBCZ
Szczegółowy opis  14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9739BBCZ Arkusz danych(HTML) 2 Page - Analog Devices

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AD9739
Data Sheet
Rev. B | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
General Description ......................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
Product Highlights ........................................................................... 1
 
Revision History ............................................................................... 2
 
Specifications..................................................................................... 4
 
DC Specifications ......................................................................... 4
 
LVDS Digital Specifications ........................................................ 5
 
Serial Port Specifications ............................................................. 6
 
AC Specifications.......................................................................... 7
 
Absolute Maximum Ratings............................................................ 8
 
Thermal Resistance ...................................................................... 8
 
ESD Caution.................................................................................. 8
 
Pin Configurations and Function Descriptions ........................... 9
 
Typical Performance Characteristics ........................................... 12
 
AC (Normal Mode).................................................................... 12
 
AC (Mix Mode) .......................................................................... 15
 
Terminology .................................................................................... 17
 
Serial Port Interface (SPI) Register............................................... 18
 
SPI Register Map Description................................................... 18
 
SPI Operation.............................................................................. 18
 
SPI Register Map............................................................................. 20
 
SPI Port Configuration and Software Reset............................ 22
 
Power-Down LVDS Interface and TxDAC®............................ 22
 
Controller Clock Disable........................................................... 22
 
Interrupt Request (IRQ) Enable/Status ................................... 22
 
TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 23
 
TxDAC Quad-Switch Mode of Operation .............................. 23
 
DCI Phase Alignment Status .................................................... 23
 
SYNC_IN Phase Alignment Status .......................................... 23
 
Data Receiver Controller Configuration................................. 23
 
Data Receiver Controller_Data Sample Delay Value ............ 24
 
Data and Sync Receiver Controller_DCI Delay
Value/Window and Phase Rotation......................................... 24
 
Data Receiver Controller_Delay Line Status and Sync
Controller SYNC_OUT Status ................................................. 24
 
Sync and Data Receiver Controller Lock/Tracking Status.... 25
 
CLK Input Common Mode ...................................................... 25
 
Mu Controller Configuration and Status................................ 25
 
Part ID ......................................................................................... 26
 
Theory of Operation ...................................................................... 27
 
LVDS Data Port Interface.......................................................... 28
 
Mu Controller ............................................................................. 32
 
Interrupt Requests...................................................................... 34
 
Multiple Device Synchronization............................................. 35
 
Analog Interface Considerations.................................................. 38
 
Analog Modes of Operation ..................................................... 38
 
Clock Input Considerations...................................................... 39
 
Voltage Reference ....................................................................... 40
 
Analog Outputs .......................................................................... 40
 
Nonideal Spectral Artifacts....................................................... 43
 
Lab Evaluation of the AD9739 ................................................. 44
 
Power Dissipation and Supply Domains................................. 44
 
Recommended Start-Up Sequence .......................................... 45
 
Outline Dimensions ....................................................................... 48
 
Ordering Guide .......................................................................... 48
 
REVISION HISTORY
1/12—Rev. A to Rev. B
Changes to Features Section, Applications Section, General
Description Section, Figure 1, Product Highlights Section........ 1
Changes to DC Specifications Section........................................... 4
Changed Digital Specifications Section to LVDS Digital
Specifications Section....................................................................... 5
Changes to LVDS Digital Specifications Section ......................... 5
Added Serial Port Specifications Section and Table 3;
Renumbered Sequentially................................................................ 6
Changes to AC Specifications Section ........................................... 7
Changes to Table 5............................................................................ 8
Changes to Table 7.......................................................................... 10
Deleted Static Linearity Section and Figure 7 to Figure 17;
Renumbered Sequentially ............................................................. 11
Changed Dynamic Performance Normal Mode, 20 mA Full
Scale (Unless Otherwise Noted) Section to AC (Normal Mode)
Section.............................................................................................. 12
Changes to AC (Normal Mode) Section ..................................... 12
Changed Dynamic Performance Mix Mode, 20 mA Full Scale
Section to AC (Mix Mode) Section.............................................. 15
Changes to AC (Mix Mode) Section............................................ 15
Added Serial Port Interface (SPI) Register Section, SPI Register
Map Description Section, Reset Section, Table 8, and SPI
Operation Section and Figure 34 ................................................. 18


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