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ADSP-2181BST-115 Arkusz danych(PDF) 8 Page - Analog Devices |
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ADSP-2181BST-115 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 32 page REV. D ADSP-2181 –8– The CMS pin functions like the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits, except the BMS bit, default to 1 at reset. Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-2181 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA) The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally, and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate num- ber of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit. Table V. Internal BTYPE Memory Space Word Size Alignment 00 Program Memory 24 Full Word 01 Data Memory 16 Full Word 10 Data Memory 8 MSBs 11 Data Memory 8 LSBs Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the start- ing page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is gener- ated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of MMAP, PMOVLAY or DMOVLAY. There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. Table III. DMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x0000 and 0x1FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x0000 and 0x1FFF This organization allows for two external 8K overlays using only the normal 14 address bits. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. I/O Space The ADSP-2181 supports an additional external memory space called I/O space. This space is designed to support simple con- nections to peripherals or to bus interface ASIC data registers. I/O space supports 2048 locations. The lower eleven bits of the external address bus are used; the upper three bits are unde- fined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV. Table IV. Address Range Wait State Register 0x000–0x1FF IOWAIT0 0x200–0x3FF IOWAIT1 0x400–0x5FF IOWAIT2 0x600–0x7FF IOWAIT3 Composite Memory Select ( CMS) The ADSP-2181 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals ( PMS, DMS, BMS, IOMS) but can combine their functionality. When set, each bit in the CMSSEL register, causes the CMS signal to be asserted when the selected memory select is as- serted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory; use either DMS or PMS as the additional address bit. |
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