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AD1852JRSZRL Arkusz danych(PDF) 5 Page - Analog Devices |
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AD1852JRSZRL Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 20 page AD1852 Rev. A | Page 5 of 20 DIGITAL TIMING Guaranteed over 0°C to 70°C, AVDD = DVDD = 5.0 V × 10%. Table 8. Parameter Description Min Unit tDMP MCLK period (fMCLK = 256 × fLRCLK)1 54 ns tDML MCLK low pulse width (all modes) 0.4 × tDMP ns tDMH MCLK high pulse width (all modes) 0.4 × tDMP ns tDBH BCLK high pulse width (see Figure 26) 20 ns tDBL BCLK low pulse width (see Figure 26) 20 ns tDBP BCLK period (see Figure 26) 60 ns tDLS LRCLK setup (see Figure 26) 20 ns tDLH LRCLK hold (DSP serial port mode only) 5 ns tDDS SDATA setup (see Figure 26) 5 ns tDDH SDATA hold (see Figure 26) 10 ns tRSTL RESET low pulse width 15 ns 1 Higher MCLK frequencies are allowable when using the on-chip master clock autodivide feature. |
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