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AD5162BRM100-RL7 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD5162BRM100-RL7 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 20 page AD5162 Rev. C | Page 5 of 20 TIMING CHARACTERISTICS: ALL VERSIONS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit SPI INTERFACE TIMING CHARACTERISTICS1 Clock Frequency f CLK 25 MHz Input Clock Pulse Width t CH, tCL Clock level high or low 20 ns Data Setup Time t DS 5 ns Data Hold Time t DH 5 ns CS t CSS Setup Time 15 ns CS t CSW High Pulse Width 40 ns CLK Fall to CS t CSH0 Fall Hold Time 0 ns CLK Fall to CS t CSH1 Rise Hold Time 0 ns CS t CS1 Rise to Clock Rise Setup 10 ns 1 See the timing diagrams for the locations of measured values (that is, see Figure 42 and Figure 43). |
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