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AD7564BRS-REEL Arkusz danych(PDF) 11 Page - Analog Devices |
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AD7564BRS-REEL Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 17 page –11– REV. 3 AD7564 GENERAL DESCRIPTION D/A Section The AD7564 contains four 12-bit current output D/A convert- ers. A simplified circuit diagram for one of the D/A converters is shown in Figure 15. VREF 2R 2R 2R 2R 2R 2R 2R CB A S9 S8 S0 RFB I OUT1 I OUT2 R R R R/2 SHOWN FOR ALL 1s ON DAC Figure 15. Simplified D/A Circuit Diagram A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A, B and C. The remaining 10 bits of the data word drive the switches S0 to S9 in a standard R-2R ladder configuration. Each of the switches A to C steers 1/4 of the total reference current with the remaining current passing through the R-2R section. All DACs have separate VREF, IOUT1, IOUT2 and RFB pins. When an output amplifier is connected in the standard configu- ration of Figure 17, the output voltage is given by: VOUT = D ×VREF where D is the fractional representation of the digital word loaded to the DAC. Thus, in the AD7564, D can be set from 0 to 4095/4096. Interface Section The AD7564 is a serial input device. Three input signals con- trol the serial interface. These are FSIN, CLKIN and SDIN. The timing diagram is shown in Figure 1. Data applied to the SDIN pin is clocked into the input shift reg- ister on each falling edge of CLKIN. SDOUT is the shift regis- ter output. It allows multiple devices to be connected in a daisy chain fashion with the SDOUT pin of one device connected to the SDIN of the next device. FSIN is the frame synchronization for the device. When the sixteen bits have been received in the input shift regis- ter, DB2 and DB3 (A0 and A1) are checked to see if they corre- spond to the state on pins A0 and A1. If it does, then the word is accepted. Otherwise, it is disregarded. This allows the user to address a number of AD7564s in a very simple fashion. DB1 and DB0 of the 16-bit word determine which of the four DAC input latches is to be loaded. When the LDAC line goes low, all four DAC latches in the device are simultaneously loaded with the contents of their respective input latches and the outputs change accordingly. Bringing the CLR line low resets the DAC latches to all 0s. The input latches are not affected so that the user can revert to the previous analog output if desired. 16-BIT INPUT SHIFT REGISTER CLKIN FSIN SDIN SDOUT Figure 16. Input Logic UNIPOLAR BINARY OPERATION (2-Quadrant Multiplication) Figure 17 shows the standard unipolar binary connection dia- gram for one of the DACs in the AD7564. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Resistors R1 and R2 allow the user to adjust the DAC gain error. Offset can be removed by adjusting the output amplifier offset voltage. Figure 17. Unipolar Binary Operation A1 should be chosen to suit the application. For example, the AD707 is ideal for very low bandwidth applications while the AD843 and AD845 offer very fast settling time in wide band- width applications. Appropriate multiple versions of these am- plifiers can be used with the AD7564 to reduce board space requirements. The code table for Figure 17 is shown in Table III. Table III. Unipolar Binary Code Table Digital Input Analog Output MSB . . . LSB (VOUT as Shown in Figure 17) 1111 1111 1111 –VREF (4095/4096) 1000 0000 0001 –VREF (2049/4096) 1000 0000 0000 –VREF (2048/4096) 0111 1111 1111 –VREF (2047/4096) 0000 0000 0001 –VREF (1/4096) 0000 0000 0000 –VREF (0/4096) = 0 NOTE Nominal LSB size for the circuit of Figure 17 is given by: VREF (1/4096). DAC A A1 AD7564 VREFA VIN NOTES 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER. R2 10 Ω R1 20 Ω SIGNAL GND A1: AD707 AD711 AD843 AD845 C1 RFBA IOUT2A IOUT1A VOUT B |
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