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ADXL350BCEZ-RL Arkusz danych(PDF) 28 Page - Analog Devices

Numer części ADXL350BCEZ-RL
Szczegółowy opis  Digital Accelerometer
Download  36 Pages
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Strona internetowa  http://www.analog.com
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ADXL350BCEZ-RL Arkusz danych(HTML) 28 Page - Analog Devices

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ADXL350
Data Sheet
Rev. 0 | Page 28 of 36
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor
(CIO) at VDDI/O placed close to the ADXL350 supply pins is used
for testing and is recommended to adequately decouple the
accelerometer from noise on the power supply. If additional
decoupling is necessary, a resistor or ferrite bead, no larger than
100 Ω, in series with VS may be helpful. Additionally, increasing
the bypass capacitance on VS to a 10 μF tantalum capacitor in
parallel with a 0.1 μF ceramic capacitor may also improve noise.
Care should be taken to ensure that the connection from the
ADXL350 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar
to noise transmitted through VS. It is recommended that VS and
VDDI/O be separate supplies to minimize digital clocking noise
on the VS supply. If this is not possible, additional filtering of
the supplies as previously mentioned may be necessary.
ADXL350
GND
INT1
INT2
CS
SCL/SCLK
SDO/ALT ADDRESS
SDA/SDI/SDIO
3- OR 4-WIRE
SPI OR I2C
INTERFACE
VS
VS
CS
VDD I/O
VDD I/O
CIO
INTERRUPT
CONTROL
Figure 58. Application Diagram
MECHANICAL CONSIDERATIONS FOR MOUNTING
The ADXL350 should be mounted on the PCB in a location
close to a hard mounting point of the PCB to the case. Mounting
the ADXL350 at an unsupported PCB location, as shown in
Figure 59, may result in large, apparent measurement errors due
to undampened PCB vibration. Locating the accelerometer near
a hard mounting point ensures that any PCB vibration at the
accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer.
MOUNTING POINTS
PCB
ACCELEROMETERS
Figure 59. Incorrectly Placed Accelerometers
TAP DETECTION
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 60
for a valid single and valid double tap event:
The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
The maximum tap duration time is defined by the DUR
register (Address 0x21).
The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end of
the first tap until the start of the time window, when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
FIRST TAP
TIME LIMIT FOR
TAPS (DUR)
LATENCY
TIME
(LATENT)
TIME WINDOW FOR
SECOND TAP (WINDOW)
SECOND TAP
SINGLE TAP
INTERRUPT
DOUBLE TAP
INTERRUPT
THRESHOLD
(THRESH_TAP)
Figure 60. Tap Interrupt Function with Valid Single and Double Taps
If only the single tap function is in use, the single tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
tap functions are in use, the single tap interrupt is triggered when
the double tap event has been either validated or invalidated.
Several events can occur to invalidate the second tap of a double
tap event. First, if the suppress bit in the TAP_AXES register
(Address 0x2A) is set, any acceleration spike above the threshold
during the latency time (set by the latent register) invalidates
the double tap detection, as shown in Figure 61.
INVALIDATES DOUBLE TAP IF
SUPRESS BIT SET
TIME WINDOW FOR SECOND
TAP (WINDOW)
LATENCY
TIME (LATENT)
TIME LIMIT
FOR TAPS
(DUR)
Figure 61. Double Tap Event Invalid Due to High g Event
When the Suppress Bit Is Set


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