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ADXL350BCEZ-RL Arkusz danych(PDF) 17 Page - Analog Devices

Numer części ADXL350BCEZ-RL
Szczegółowy opis  Digital Accelerometer
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Strona internetowa  http://www.analog.com
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ADXL350BCEZ-RL Arkusz danych(HTML) 17 Page - Analog Devices

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Data Sheet
ADXL350
Rev. 0 | Page 17 of 36
Table 9. SPI Digital Input/Output Voltage
Limit1
Parameter
Test Conditions
Min
Max
Unit
Digital Input
Low Level Input Voltage (V
IL)
0.3 × V
DD I/O
V
High Level Input Voltage (V
IH)
0.7 × V
DD I/O
V
Low Level Input Current (I
IL)
V
IN = VDD I/O
0.1
µA
High Level Input Current (I
IH)
V
IN = 0 V
−0.1
µA
Digital Output
Low Level Output Voltage (V
OL)
I
OL = 10 mA
0.2 × V
DD I/O
V
High Level Output Voltage (V
OH)
I
OH = −4 mA
0.8 × V
DD I/O
V
Low Level Output Current (I
OL)
V
OL = VOL, max
10
mA
High Level Output Current (I
OH)
V
OH = VOH, min
−4
mA
Pin Capacitance
f
IN = 1 MHz, VIN = 2.5 V
8
pF
1 Limits based on characterization results, not production tested.
Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDDI/O= 1.8 V)1
Limit2, 3
Parameter
Min
Max
Unit
Description
f
SCLK
5
MHz
SPI clock frequency
t
SCLK
200
ns
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
t
DELAY
10
ns
CS falling edge to SCLK falling edge
t
QUIET
10
ns
SCLK rising edge to CS rising edge
t
DIS
100
ns
CS rising edge to SDO disabled
t
CS,DIS
250
ns
CS deassertion between SPI communications
t
S
0.4 × t
SCLK
ns
SCLK low pulse width (space)
t
M
0.4 × t
SCLK
ns
SCLK high pulse width (mark)
t
SDO
95
ns
SCLK falling edge to SDO transition
t
SETUP
10
ns
SDI valid before SCLK rising edge
t
HOLD
10
ns
SDI valid after SCLK rising edge
1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2 Limits are based on characterization results, characterized with f
SCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3 The timing values are measured corresponding to the input thresholds (V
IL and VIH) given in Table 9.


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