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ADXL350BCEZ-RL Arkusz danych(PDF) 20 Page - Analog Devices |
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ADXL350BCEZ-RL Arkusz danych(HTML) 20 Page - Analog Devices |
20 / 36 page ADXL350 Data Sheet Rev. 0 | Page 20 of 36 Table 12. I2C Timing (TA = 25°C, VS = 2.5 V, VDDI/O= 1.8 V) Limit1, 2 Parameter Min Max Unit Description f SCL 400 kHz SCL clock frequency t 1 2.5 µs SCL cycle time t 2 0.6 µs t HIGH, SCL high time t 3 1.3 µs t LOW, SCL low time t 4 0.6 µs t HD, STA, start/repeated start condition hold time t 5 350 ns t SU, DAT, data setup time t 6 3, 4, 5, 6 0 0.65 µs t HD, DAT, data hold time t 7 0.6 µs t SU, STA, setup time for repeated start t 8 0.6 µs t SU, STO, stop condition setup time t 9 1.3 µs t BUF, bus-free time between a stop condition and a start condition t 10 300 ns t R, rise time of both SCL and SDA when receiving 0 ns t R, rise time of both SCL and SDA when receiving or transmitting t 11 250 ns t F, fall time of SDA when receiving 300 ns t F, fall time of both SCL and SDA when transmitting 20 + 0.1 C b 7 ns t F, fall time of both SCL and SDA when transmitting or receiveing C b 400 pF Capacitive load for each bus line 1 Limits are based on characterization results, with f SCL = 400 kHz and a 3 mA sink current; not production tested. 2 All values are referred to the V IH and the VIL levels given in Table 11. 3 t 6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge times. 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to V IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5 The maximum t 6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 6 The maximum value for t 6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min). 7 C b is the total capacitance of one bus line in picofarads. SDA t9 SCL t3 t10 t11 t4 t4 t6 t2 t5 t7 t1 t8 START CONDITION REPEATED START CONDITION STOP CONDITION Figure 57. I2C Timing Diagram |
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