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ADXL350BCEZ-RL Arkusz danych(PDF) 22 Page - Analog Devices |
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ADXL350BCEZ-RL Arkusz danych(HTML) 22 Page - Analog Devices |
22 / 36 page ADXL350 Data Sheet Rev. 0 | Page 22 of 36 Trigger Mode In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. A delay of at least 5 μs should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO. Retrieving Data from FIFO The FIFO data is read through the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY, and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data are placed into the DATAX, DATAY, and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest should be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 μs between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS pin to ensure a total delay of 5 μs; otherwise, the delay will not be sufficient. The total delay necessary for 5 MHz operation is at most 3.4 μs. This is not a concern when using I2C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads. SELF-TEST The ADXL350 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS2, the output change varies with VS. The self-test feature of the ADXL350 also exhibits a bimodal behavior that depends on which phase of the clock self-test is enabled. However, the limits shown in Table 1 and Table 13 to Table 16 are valid for all potential self-test values across the entire allowable voltage range. Use of the self-test feature at data rates less than 100 Hz may yield values outside these limits. Therefore, the part should be placed into a data rate of 100 Hz or greater when using self-test. Table 13. Self-Test Output in LSB for ±1 g, 10-bit Resolution or any g-Range, Full Resolution Axis Min Max Unit X 100 1180 LSB Y −1180 −100 LSB Z 150 1850 LSB Table 14. Self-Test Output in LSB for ±2 g, 10-Bit Resolution Axis Min Max Unit X 50 590 LSB Y −590 −50 LSB Z 75 925 LSB Table 15. Self-Test Output in LSB for ±4 g, 10-Bit Resolution Axis Min Max Unit X 25 295 LSB Y −295 −25 LSB Z 38 463 LSB Table 16. Self-Test Output in LSB for ±8 g, 10-Bit Resolution Axis Min Max Unit X 12 148 LSB Y −148 −12 LSB Z 19 232 LSB |
Podobny numer części - ADXL350BCEZ-RL |
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Podobny opis - ADXL350BCEZ-RL |
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