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ADXL350BCEZ-RL Arkusz danych(PDF) 27 Page - Analog Devices |
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ADXL350BCEZ-RL Arkusz danych(HTML) 27 Page - Analog Devices |
27 / 36 page Data Sheet ADXL350 Rev. 0 | Page 27 of 36 Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) These six bytes (Register 0x32 to Register 0x37) are eight bits each and hold the output data for each axis. Register 0x32 and Register 0x33 hold the output data for the x-axis, Register 0x34 and Register 0x35 hold the output data for the y-axis, and Register 0x36 and Register 0x37 hold the output data for the z-axis. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers. Register 0x38—FIFO_CTL (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 FIFO_MODE Trigger Samples FIFO_MODE Bits These bits set the FIFO mode, as described in Table 20. Table 20. FIFO Modes Setting D7 D6 Mode Function 0 0 Bypass FIFO is bypassed. 0 1 FIFO FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not full. 1 0 Stream FIFO holds the last 32 data values. When FIFO is full, the oldest data is overwritten with newer data. 1 1 Trigger When triggered by the trigger bit, FIFO holds the last data samples before the trigger event and then continues to collect data until full. New data is collected only when FIFO is not full. Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to INT1, and a value of 1 links the trigger event to INT2. Samples Bits The function of these bits depends on the FIFO mode selected (see Table 21). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. Table 21. Samples Bits Functions FIFO Mode Samples Bits Function Bypass None. FIFO Specifies how many FIFO entries are needed to trigger a watermark interrupt. Stream Specifies how many FIFO entries are needed to trigger a watermark interrupt. Trigger Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event. 0x39—FIFO_STATUS (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 FIFO_TRIG 0 Entries FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. Entries Bits These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. |
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